1. Field of the Invention
The present invention relates to a method for planarization, and more particularly to a two-steps polish method for planarization.
2. Description of the Related Art
Since modern semiconductor technologies have progressed into deep submicron generation, chemical mechanical polishing (CMP) processes have became a crucial planarization process. One of the applications of the CMP process is applied in the formation of shallow trench isolation (STI). However, even though a modern CMP process could provide a satisfactory performance in the processes of device features with a critical dimension above 0.25 micron, it still could not meet the requirement of processes of device features with a critical dimension under 0.18 micron since the device features are such tiny and the accuracy of the processes must be highly and carefully controlled. To increase process margin, present CMP processes cannot be solely applied in the process of STI with a dimension under 0.18 micron without using other assistant technologies and equipments such as additional etching processes and reverse masks. FIG. 1A to FIG. 1D show a conventional CMP process for a STI planarization. As shown in FIG. 1A, a re-fill oxide layer 104 is conformally formed over a substrate 100 having a trench therein and a dielectric layer 102 thereon. Then as shown in FIG. 1B, a photoresist layer 106 is formed and is patterned by a reverse mask process to define a STI. Next as shown in FIG. 1C, the re-fill oxide layer 104 is anisotropically etched to a predetermined thickness. Finally, the re-fill oxide layer 104 is planarized to expose the dielectric layer 102 by a CMP process as shown in FIG. 1D.
However, the conventional CMP process for a STI planarization shown in FIG. 1A to FIG. 1D still has several advantages even though it is one of the few practical solutions of tiny feature planarization issues. For example, the use of the reverse mask and additional etching process would increase production cost and process complexity, and the composite process would gradually not be suitable for the process of tiny device features with continuously shrinking line width and increasing pattern density.
The performance of planarization of conventional CMP processes is limited by the thickness control of the re-fill oxide layer. Especially, when the trench size is about deep submicron level, the performance of planarization of conventional CMP processes would be degraded by the variation of the over-fill thickness of the re-fill oxide layer since the thickness control of the re-fill oxide layer is tough. As shown in FIG. 2A and FIG. 2B, the over-fill thickness of a re-fill oxide layer 202 over a trench usually presents apparent variety at the edge (FIG. 2A) and the center (FIG. 2B ) of a chip. The re-fill oxide layer 202 even presents vacancy over a trench without a over-fill thickness. The non-uniformity of the over-fill thickness of the re-fill oxide layer 202 would render the planarization capability of the CMP process failure.
Thus it is necessary to provide a new method to improve the planarization capability of modern CMP processes, meanwhile, maintains simplicity and low cost of the CMP processes. It is towards those goals that the present invention is specifically directed.